#include <arch/cache.h>
Go to the source code of this file.
Data Structures | |||||
| struct | classes | ||||
| PCI device class structure. It is used to recognize to what class a device belongs. More... | |||||
| struct | confadd | ||||
| A structure to write to the PCI configuration register. It represents a location on the PCI bus. More... | |||||
| struct | pci_cfg | ||||
| PCI configuration structure for a device. Every PCI device belong to a known class. To find this class we have to look at the base_class, sub_class and interface code. More... | |||||
Defines | |||||
| #define | PCI_HEADER_TYPE_NORMAL 0 | ||||
| This is a normal PCI device. | |||||
| #define | PCI_HEADER_TYPE_BRIDGE 1 | ||||
| This is a bridge PCI device. | |||||
| #define | PCI_HEADER_TYPE_CARDBUS 2 | ||||
| This is a card-bus PCI device. | |||||
| #define | PCI_STATUS_CAP_LIST 0x10 | ||||
| Support capability list. | |||||
| #define | PCI_COMMAND 0x04 | ||||
| PCI command register (offset). | |||||
| #define | PCI_STATUS 0x06 | ||||
| PCI status register (offset). | |||||
| #define | PCI_INTERRUPT_LINE 0x3C | ||||
| PCI interrupt line register (offset). | |||||
| #define | PCI_INTERRUPT_PIN 0x3D | ||||
| PCI interrupt pin register (offset). | |||||
| #define | PCI_SUBSYSTEM_VENDOR_ID 0x2C | ||||
| PCI subsystem vendor id register (offset). | |||||
| #define | PCI_SUBSYSTEM_ID 0x2E | ||||
| PCI subsystem id register (offset). | |||||
| #define | PCI_LATENCY_TIMER 0x0D | ||||
| PCI latency timer register (offset). | |||||
| #define | PCI_CAPABILITY_LIST 0x34 | ||||
| PCI of first capability list entry (offset). | |||||
| #define | PCI_CB_CAPABILITY_LIST 0x14 | ||||
| PCI of first capability list cardbus (offset). | |||||
| #define | PCI_CACHE_LINE_SIZE 0x0C | ||||
| The PCI cache line size register (offset). | |||||
| #define | PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 | ||||
| The PCI subsystem vendor id register for cardbus (offset). | |||||
| #define | PCI_CB_SUBSYSTEM_ID 0x42 | ||||
| The PCI subsystem id register for cardbuses (offset). | |||||
| #define | PCI_ROM_ADDRESS 0x30 | ||||
| The PCI ROM address register for normal devices (offset). | |||||
| #define | PCI_ROM_ADDRESS_1 0x38 | ||||
| The PCI ROM address register for PCI to PCI bridges (offset). | |||||
| #define | PCI_PM_PMC 2 | ||||
| Power Management capabilities register. | |||||
| #define | PCI_PM_CTRL 4 | ||||
| Power Management control and status register. | |||||
| #define | PCI_PM_CAP_D1 0x0200 | ||||
| D1 power state support. | |||||
| #define | PCI_PM_CAP_D2 0x0400 | ||||
| D2 power state support. | |||||
| #define | PCI_ROM_ADDRESS_ENABLE 0x01 | ||||
| Enable ROM address. | |||||
| #define | PCI_COMMAND_IO 0x01 | ||||
| The device is I/O-based (a.k.a. can perform I/O operations using the ports). | |||||
| #define | PCI_COMMAND_MEMORY 0x02 | ||||
| The device is memory-based (a.k.a. can perform I/O operations by a memory-mapped buffer). | |||||
| #define | PCI_COMMAND_MASTER 0x04 | ||||
| Enable bus master (a.k.a. 32-bit DMA). | |||||
| #define | PCI_BASE_ADDRESS_0 0x10 | ||||
| First base address register. Every PCI device has up to 6 base addresses (6 for normal devices, 2 for PCI to PCI bridges and only 1 for cardbuses). | |||||
| #define | PCI_BASE_ADDRESS_SPACE 0x01 | ||||
| The base address is I/O-based (a.k.a. it is a port value). | |||||
| #define | PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 | ||||
| The base address is memory-based (a.k.a. it is a memory address value). | |||||
| #define | PCI_IO_RESOURCE_MEM 0x00 | ||||
| The device is memory-based (a.k.a. can perform I/O operations by a memory-mapped buffer). | |||||
| #define | PCI_IO_RESOURCE_IO 0x01 | ||||
| The device is I/O-based (a.k.a. can perform I/O operations using the ports). | |||||
| #define | PCI_CAP_LIST_ID 0 | ||||
| Capability ID. | |||||
| #define | PCI_CAP_ID_PM 0x01 | ||||
| Power Management. | |||||
| #define | PCI_CAP_ID_AGP 0x02 | ||||
| Accelerated Graphics Port. | |||||
| #define | PCI_CAP_ID_VPD 0x03 | ||||
| Vital Product Data. | |||||
| #define | PCI_CAP_ID_SLOTID 0x04 | ||||
| Slot Identification. | |||||
| #define | PCI_CAP_ID_MSI 0x05 | ||||
| Message Signalled Interrupts. | |||||
| #define | PCI_CAP_ID_CHSWP 0x06 | ||||
| CompactPCI HotSwap. | |||||
| #define | PCI_CAP_LIST_NEXT 1 | ||||
| Next capability in the list. | |||||
| #define | PCI_CAP_FLAGS 2 | ||||
| Capability defined flags (16-bits). | |||||
| #define | PCI_CAP_SIZEOF 4 | ||||
| Size of PCI capability. | |||||
| #define | PCI_ROM_ADDRESS_MASK (~0x7FFUL) | ||||
| PCI ROM address mask. | |||||
| #define | PCI_BASE_ADDRESS_MEM_MASK (~0x0FUL ) | ||||
| PCI base address mask (for memory-based devices). | |||||
| #define | PCI_BASE_ADDRESS_IO_MASK (~0x03UL ) | ||||
| PCI base address mask (for I/O-based devices). | |||||
| #define | PCI_PM_CTRL_STATE_MASK ( 0x0003 ) | ||||
| Current power state (D0 to D3). | |||||
Typedefs | |||||
| typedef confadd | confadd_t | ||||
| A structure to write to the PCI configuration register. It represents a location on the PCI bus. | |||||
| typedef const struct classes | classes_t | ||||
| PCI device class structure. It is used to recognize to what class a device belongs. | |||||
| typedef pci_cfg | pci_cfg_t | ||||
| PCI configuration structure for a device. Every PCI device belong to a known class. To find this class we have to look at the base_class, sub_class and interface code. | |||||
Functions | |||||
| bool | pci_find_cfg (pci_cfg_t *cfg, bool enable) | ||||
Look for a device in the PCI bus and eventually enable it.
| |||||
| void | pci_scan () | ||||
| Scan all the PCI buses, looking for devices. If a device is found it will be enabled. | |||||
Definition in file pci.h.
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First base address register. Every PCI device has up to 6 base addresses (6 for normal devices, 2 for PCI to PCI bridges and only 1 for cardbuses).
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PCI base address mask (for I/O-based devices).
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PCI base address mask (for memory-based devices).
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The base address is I/O-based (a.k.a. it is a port value).
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The base address is memory-based (a.k.a. it is a memory address value).
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The PCI cache line size register (offset).
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Capability defined flags (16-bits).
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Accelerated Graphics Port.
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CompactPCI HotSwap.
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Message Signalled Interrupts.
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Power Management.
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Slot Identification.
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Vital Product Data.
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Capability ID.
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Next capability in the list.
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Size of PCI capability.
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PCI of first capability list entry (offset).
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PCI of first capability list cardbus (offset).
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The PCI subsystem id register for cardbuses (offset).
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The PCI subsystem vendor id register for cardbus (offset).
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PCI command register (offset).
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The device is I/O-based (a.k.a. can perform I/O operations using the ports).
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Enable bus master (a.k.a. 32-bit DMA).
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The device is memory-based (a.k.a. can perform I/O operations by a memory-mapped buffer).
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This is a bridge PCI device.
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This is a card-bus PCI device.
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This is a normal PCI device.
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PCI interrupt line register (offset).
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PCI interrupt pin register (offset).
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The device is I/O-based (a.k.a. can perform I/O operations using the ports).
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The device is memory-based (a.k.a. can perform I/O operations by a memory-mapped buffer).
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PCI latency timer register (offset).
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D1 power state support.
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D2 power state support.
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Power Management control and status register.
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Current power state (D0 to D3).
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Power Management capabilities register.
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The PCI ROM address register for normal devices (offset).
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The PCI ROM address register for PCI to PCI bridges (offset).
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Enable ROM address.
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PCI ROM address mask.
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PCI status register (offset).
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Support capability list.
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PCI subsystem id register (offset).
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PCI subsystem vendor id register (offset).
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PCI device class structure. It is used to recognize to what class a device belongs.
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A structure to write to the PCI configuration register. It represents a location on the PCI bus.
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1.2.18