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Data Structures |
struct | Device_Struct |
struct | DeviceInfo_Struct |
struct | IdeChannel_Struct |
Defines |
#define | HDC_BASEPRI 0x1F0 |
#define | HDC_BASESEC 0x170 |
#define | HDC_CONTROLGAP 0x200 |
#define | HDC_INTPRI 14 |
#define | HDC_INTSEC 15 |
#define | HDC_DATA 0 |
#define | HDC_ERR 1 |
#define | HDC_SECC 2 |
#define | HDC_SECN 3 |
#define | HDC_CYLL 4 |
#define | HDC_CYLH 5 |
#define | HDC_DEVH 6 |
#define | HDC_STATUS 7 |
#define | HDC_ASTAT 6 |
#define | HDC_ADD 7 |
#define | HDC_DEVH_OBSOLETE 0xa0 |
#define | HDC_DEVH_DEV0 HDC_DEVH_OBSOLETE | 0x00 |
#define | HDC_DEVH_DEV1 HDC_DEVH_OBSOLETE | 0x10 |
#define | HDC_DEVH_LBA 0x40 |
#define | HDC_DEVC_HD15 0x08 |
#define | HDC_DEVC_SRST 0x04 |
#define | HDC_DEVC_NIEN 0x02 |
#define | HDC_STAT_BSY 0x80 |
#define | HDC_STAT_RDY 0x40 |
#define | HDC_STAT_DF 0x20 |
#define | HDC_STAT_WFT 0x20 |
#define | HDC_STAT_SKC 0x10 |
#define | HDC_STAT_SERV 0x10 |
#define | HDC_STAT_DRQ 0x08 |
#define | HDC_STAT_CORR 0x04 |
#define | HDC_STAT_IDX 0x02 |
#define | HDC_STAT_ERR 0x01 |
#define | HDC_STAT_CHK 0x01 |
#define | HDC_CMD_CFA_ERASE_SECTORS 0xC0 |
#define | HDC_CMD_CFA_REQUEST_EXT_ERR_CODE 0x03 |
#define | HDC_CMD_CFA_TRANSLATE_SECTOR 0x87 |
#define | HDC_CMD_CFA_WRITE_MULTIPLE_WO_ERASE 0xCD |
#define | HDC_CMD_CFA_WRITE_SECTORS_WO_ERASE 0x38 |
#define | HDC_CMD_CHECK_POWER_MODE1 0xE5 |
#define | HDC_CMD_CHECK_POWER_MODE2 0x98 |
#define | HDC_CMD_DEVICE_RESET 0x08 |
#define | HDC_CMD_EXECUTE_DEVICE_DIAGNOSTIC 0x90 |
#define | HDC_CMD_FLUSH_CACHE 0xE7 |
#define | HDC_CMD_FORMAT_TRACK 0x50 |
#define | HDC_CMD_IDENTIFY_DEVICE 0xEC |
#define | HDC_CMD_IDENTIFY_PACKET_DEVICE 0xA1 |
#define | HDC_CMD_IDLE1 0xE3 |
#define | HDC_CMD_IDLE2 0x97 |
#define | HDC_CMD_IDLE_IMMEDIATE1 0xE1 |
#define | HDC_CMD_IDLE_IMMEDIATE2 0x95 |
#define | HDC_CMD_INITIALIZE_DRIVE_PARAMETERS 0x91 |
#define | HDC_CMD_INITIALIZE_DEVICE_PARAMETERS 0x91 |
#define | HDC_CMD_NOP 0x00 |
#define | HDC_CMD_PACKET 0xA0 |
#define | HDC_CMD_READ_BUFFER 0xE4 |
#define | HDC_CMD_READ_DMA 0xC8 |
#define | HDC_CMD_READ_DMA_QUEUED 0xC7 |
#define | HDC_CMD_READ_MULTIPLE 0xC4 |
#define | HDC_CMD_READ_SECTORS 0x20 |
#define | HDC_CMD_READ_VERIFY_SECTORS 0x40 |
#define | HDC_CMD_RECALIBRATE 0x10 |
#define | HDC_CMD_SEEK 0x70 |
#define | HDC_CMD_SET_FEATURES 0xEF |
#define | HDC_CMD_SET_MULTIPLE_MODE 0xC6 |
#define | HDC_CMD_SLEEP1 0xE6 |
#define | HDC_CMD_SLEEP2 0x99 |
#define | HDC_CMD_STANDBY1 0xE2 |
#define | HDC_CMD_STANDBY2 0x96 |
#define | HDC_CMD_STANDBY_IMMEDIATE1 0xE0 |
#define | HDC_CMD_STANDBY_IMMEDIATE2 0x94 |
#define | HDC_CMD_WRITE_BUFFER 0xE8 |
#define | HDC_CMD_WRITE_DMA 0xCA |
#define | HDC_CMD_WRITE_DMA_QUEUED 0xCC |
#define | HDC_CMD_WRITE_MULTIPLE 0xC5 |
#define | HDC_CMD_WRITE_SECTORS 0x30 |
#define | HDC_CMD_WRITE_VERIFY 0x3C |
Typedefs |
typedef DeviceInfo_Struct | DeviceInfo_Struct |
typedef Device_Struct | Device_Struct |
typedef IdeChannel_Struct | IdeChannel_Struct |
Functions |
void | SetAtaRegisterIoPort (word CmdBase, word CntBase, int IntN) |
void | SelectAtaChannel (int Channel) |
word | AtaPort (word Port) |
void | OutPortAta (word Port, byte Val) |
byte | InPortAta (word Port) |
void | InPortAtaMul (word Port, word *Buffer, word Count) |
void | OutPortAtaMul (word Port, word *Buffer, word Count) |
void | SetDevBit (int Dev) |
void | SetFirstDevBit () |
void | Ide_Handler (word Irq) |