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pci.h

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00001 /*!     \file include/kernel/pci.h
00002  *      \brief PCI bus driver header.
00003  *      \author Andrea Righi <drizzt@inwind.it>
00004  *      \date Last update: 2003-11-09
00005  *      \note Copyright (&copy;) 2003 Andrea Righi
00006  *
00007  *      \n
00008  *      To make this driver I have gotten some information from
00009  *      "Linux" and "The Mobius" drivers. Thanks!\n
00010  *      -Andrea Righi.
00011  */
00012 
00013 #ifndef PCI_H
00014 #define PCI_H
00015 
00016 #include <arch/cache.h>
00017 
00018 //! A structure to write to the PCI configuration register.
00019 //! It represents a location on the PCI bus.
00020 typedef struct confadd
00021 {
00022     uint8_t reg:8;
00023     uint8_t func:3;
00024     uint8_t dev:5;
00025     uint8_t bus:8;
00026     uint8_t rsvd:7;
00027     uint8_t enable:1;
00028 } confadd_t;
00029 
00030 //! PCI device class structure. It is used to recognize to what
00031 //! class a device belongs.
00032 typedef const struct classes
00033 {
00034     uint8_t base_class; //!< The base class code.
00035     uint8_t sub_class;  //!< The sub class code.
00036     uint8_t interface;  //!< The interface code.
00037     const char *name;   //!< The class name.
00038 } classes_t;
00039 
00040 //! This is a normal PCI device.
00041 #define PCI_HEADER_TYPE_NORMAL          0
00042 //! This is a bridge PCI device.
00043 #define PCI_HEADER_TYPE_BRIDGE          1
00044 //! This is a card-bus PCI device.
00045 #define PCI_HEADER_TYPE_CARDBUS         2
00046 
00047 //! Support capability list.
00048 #define PCI_STATUS_CAP_LIST             0x10
00049 
00050 // --- PCI registers -------------------------------------------------- //
00051 
00052 //! PCI command register (offset).
00053 #define PCI_COMMAND                     0x04
00054 //! PCI status register (offset).
00055 #define PCI_STATUS                      0x06
00056 //! PCI interrupt line register (offset).
00057 #define PCI_INTERRUPT_LINE              0x3C
00058 //! PCI interrupt pin register (offset).
00059 #define PCI_INTERRUPT_PIN               0x3D
00060 //! PCI subsystem vendor id register (offset).
00061 #define PCI_SUBSYSTEM_VENDOR_ID         0x2C
00062 //! PCI subsystem id register (offset).
00063 #define PCI_SUBSYSTEM_ID                0x2E
00064 //! PCI latency timer register (offset).
00065 #define PCI_LATENCY_TIMER               0x0D
00066 //! PCI of first capability list entry (offset).
00067 #define PCI_CAPABILITY_LIST             0x34
00068 //! PCI of first capability list cardbus (offset).
00069 #define PCI_CB_CAPABILITY_LIST          0x14
00070 //! The PCI cache line size register (offset).
00071 #define PCI_CACHE_LINE_SIZE             0x0C
00072 //! The PCI subsystem vendor id register for cardbus (offset).
00073 #define PCI_CB_SUBSYSTEM_VENDOR_ID      0x40
00074 //! The PCI subsystem id register for cardbuses (offset).
00075 #define PCI_CB_SUBSYSTEM_ID             0x42
00076 //! The PCI ROM address register for normal devices (offset).
00077 #define PCI_ROM_ADDRESS                 0x30
00078 //! The PCI ROM address register for PCI to PCI bridges (offset).
00079 #define PCI_ROM_ADDRESS_1               0x38
00080 
00081 // --- Power Management registers ------------------------------------- //
00082 
00083 //! Power Management capabilities register.
00084 #define PCI_PM_PMC                      2
00085 //! Power Management control and status register
00086 #define PCI_PM_CTRL                     4
00087 
00088 // --- Supported features --------------------------------------------- //
00089 
00090 //! D1 power state support.
00091 #define PCI_PM_CAP_D1                   0x0200
00092 //! D2 power state support.
00093 #define PCI_PM_CAP_D2                   0x0400
00094 
00095 // --- Actions -------------------------------------------------------- //
00096 
00097 //! Enable ROM address.
00098 #define PCI_ROM_ADDRESS_ENABLE          0x01
00099 //! The device is I/O-based (a.k.a. can perform I/O operations
00100 //! using the ports).
00101 #define PCI_COMMAND_IO                  0x01
00102 //! The device is memory-based (a.k.a. can perform I/O operations
00103 //! by a memory-mapped buffer)
00104 #define PCI_COMMAND_MEMORY              0x02
00105 //! Enable bus master (a.k.a. 32-bit DMA).
00106 #define PCI_COMMAND_MASTER              0x04
00107 
00108 // --- Resources ------------------------------------------------------ //
00109 
00110 //! First base address register. Every PCI device has up to 6 base
00111 //! addresses (6 for normal devices, 2 for PCI to PCI bridges and
00112 //! only 1 for cardbuses).
00113 #define PCI_BASE_ADDRESS_0              0x10
00114 //! The base address is I/O-based (a.k.a. it is a port value).
00115 #define PCI_BASE_ADDRESS_SPACE          0x01
00116 //! The base address is memory-based (a.k.a. it is a memory
00117 //! address value).
00118 #define PCI_BASE_ADDRESS_SPACE_MEMORY   0x00
00119 //! The device is memory-based (a.k.a. can perform I/O operations
00120 //! by a memory-mapped buffer).
00121 #define PCI_IO_RESOURCE_MEM             0x00
00122 //! The device is I/O-based (a.k.a. can perform I/O operations
00123 //! using the ports).
00124 #define PCI_IO_RESOURCE_IO              0x01
00125 
00126 // --- Capability lists ----------------------------------------------- //
00127 
00128 //! Capability ID.
00129 #define PCI_CAP_LIST_ID                 0
00130 //! Power Management.
00131 #define PCI_CAP_ID_PM                   0x01
00132 //! Accelerated Graphics Port.
00133 #define PCI_CAP_ID_AGP                  0x02
00134 //! Vital Product Data.
00135 #define PCI_CAP_ID_VPD                  0x03
00136 //! Slot Identification.
00137 #define PCI_CAP_ID_SLOTID               0x04
00138 //! Message Signalled Interrupts.
00139 #define PCI_CAP_ID_MSI                  0x05
00140 //! CompactPCI HotSwap.
00141 #define PCI_CAP_ID_CHSWP                0x06
00142 //! Next capability in the list.
00143 #define PCI_CAP_LIST_NEXT               1
00144 //! Capability defined flags (16-bits).
00145 #define PCI_CAP_FLAGS                   2
00146 //! Size of PCI capability.
00147 #define PCI_CAP_SIZEOF                  4
00148 
00149 // --- Masks ---------------------------------------------------------- //
00150 
00151 //! PCI ROM address mask.
00152 #define PCI_ROM_ADDRESS_MASK            (~0x7FFUL)
00153 //! PCI base address mask (for memory-based devices).
00154 #define PCI_BASE_ADDRESS_MEM_MASK       (~0x0FUL )
00155 //! PCI base address mask (for I/O-based devices).
00156 #define PCI_BASE_ADDRESS_IO_MASK        (~0x03UL )
00157 //! Current power state (D0 to D3).
00158 #define PCI_PM_CTRL_STATE_MASK          ( 0x0003 )
00159 
00160 /** \ingroup Drivers
00161  *  \defgroup PCIDriver Peripheral Component Interconnect (PCI) bus
00162  *  The PCI (Peripheral Component Interconnect) bus driver and device
00163  *  identification.
00164  *  @{
00165  */
00166 
00167 //! PCI configuration structure for a device.
00168 //! Every PCI device belong to a known class. To find this class we have
00169 //! to look at the #base_class, #sub_class and #interface code.
00170 /**
00171  *      \image html pci_config_header.jpg "The PCI configuration header"
00172  */
00173 typedef struct pci_cfg
00174 {
00175         // --- Normal header stuff ------------------------------------ //
00176         // !!! DO NOT CHANGE THIS 4 DWORD HEADER !!!                    //
00177 
00178         //! The vendor ID of this device.
00179         uint16_t vendor_id;
00180         //! The device ID of this device.
00181         uint16_t device_id;
00182 
00183         //! By writing to this field the system controls the device.
00184         uint16_t command;
00185         //! This field gives the status of the device with the
00186         //! meaning of the bits of this field set by the standard.
00187         uint16_t status;
00188 
00189         //! The revision ID of this device.
00190         uint8_t revision_id;
00191         //! The interface code of this device.
00192         uint8_t interface;
00193         //! The sub-class ID of this device.
00194         uint8_t sub_class;
00195         //! The base-class code of this device.
00196         uint8_t base_class;
00197 
00198         //! The cache line size.
00199         uint8_t cache_line_size;
00200         //! The latency timer.
00201         uint8_t latency_timer;
00202         //! The header type.
00203         uint8_t header_type;
00204         //! Build-in Self Test. If BIST is implemented,
00205         //! can write to a 1 to initiate BIST.
00206         uint8_t bist;
00207         // ------------------------------------------------------------ //
00208 
00209         // --- Device info -------------------------------------------- //
00210         // Below here you can add everything you want!                  //
00211 
00212         //! The bus number where this device resides.
00213         uint8_t bus;
00214         //! The device number where this device resides.
00215         uint8_t dev;
00216         //! The function number where this device resides.
00217         uint8_t func;
00218         //! The IRQ line (if the device has it! otherwise it is 0).
00219         //! Remeber that a PCI IRQ line can be shared between more
00220         //! than one device. This is a fetature of the PCI devices
00221         //! only. If more than one device shares a IRQ line the
00222         //! software must provide an opportune interrupt handler that
00223         //! recognizes the right device which causes the interrupt and
00224         //! switches the execution between the dedicated routines.
00225         uint8_t irq;
00226 
00227         //! Base addresses (for both I/O and memory-based devices).
00228         //! Every PCI device has up to 6 base addresses (6 for
00229         //! normal devices, 2 for PCI to PCI bridges and only 1 for
00230         //! cardbuses).
00231         uint32_t base[6];
00232         //! Size of the I/O space. For memory-based devices it is the
00233         //! size of the memory-mapped buffer; for I/O based devices it
00234         //! is the maximum offset of the ports used.
00235         uint32_t size[6];
00236         //! Type of the I/O operation (memory based or I/O based).
00237         uint8_t type[6];
00238         //! The ROM base address.
00239         uint32_t rom_base;
00240         //! The ROM memory space.
00241         uint32_t rom_size;
00242 
00243         //! Subsystem vendor ID.
00244         uint16_t subsys_vendor;
00245         //! Subsystem device ID.
00246         uint16_t subsys_device;
00247 
00248         //! Power management state (from D0 to D3).
00249         uint8_t current_state;
00250 } pci_cfg_t;
00251 
00252 // --- Prototypes ----------------------------------------------------- //
00253 
00254 bool pci_find_cfg(pci_cfg_t *cfg, bool enable);
00255 void pci_scan();
00256 
00257 /** @} */ // end of PCIDriver
00258 
00259 #endif

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